The resolution of Digital Analog Converters (DACs) can be improved, at cost of bandwidth, using dithering with error-shaping and analog low-pass filtering. The quantization noise can be moved to high frequencies and filtered by analog low-pass filter. This usually requires oversampling to compensate for bandwidth loss. This theory can be applied to create a perfect, but slow, DAC: fully linear, with arbitrary resolution (limited by digital signal processing), and arbitrary low noise (limited by analog filter design). Such approach requires a proper dithering to work to linearize the system and provide stationary noise. Usually TPDF dither is used.
Because signal processing is cheaper than hardware, 1-bit DAC is ideal for low-cost applications. Unfortunately, proper TPDF dithering cannot be applied directly to 1-bit DACs, a good dithering requires at least 3 output levels, 4 output levels to build useful DAC, and usually more levels for error-shaping.
But, what if 1-bit DAC could be changed to multi-level DAC using a different approach? Random Pattern DAC (RPDAC) probably does this. Multi-level signal (2-bit in example) is changed to random multi-cycle pattern with proper average. The pattern is chosen randomly, for constant input RPDAC will generate truly random signal built from multi-cycle patters, no signal modulation, present in PWM or not properly dithered error-shaped DAC/Sigma-delta DAC, will occur. Such >= 2-bit DAC can be used to construct higher resolution DAC using classical error-shaping.
In the simplest form rpdac.v 2-bit DAC can be constructed from 4 cycle random patterns:
| Value | Patterns |
| 00 | 0000 |
| 01 | 0001, 0010, 0100, 1000 |
| 10 | 0011, 0110, 1100, 1001, 0101, 1010 |
| 11 | 1110, 1101, 1011, 0111 |
The simplest implementation uses only up to 3 random bits per sample, for 10 input high frequency patterns: 0101 and 1010 have 2 times higher selection probability. The selection is still random, it should not generate artifacts, and even performance might be improved.
Due to dithering the DAC range must be limitted. The full DAC with ESQ limits the DAC range to (0.25, 0.50) of full output range.
N-bit DAC can be implemented on 1-bit DAC also by using fully random signal. All you need is N-bit RNG, if input value is larger than signal from generator the output is equal to one; zero otherwise. This is classical oversampling approach, with flat noise floor. However with such approach you need 4x oversampling for one bit, 16x oversampling for two bits, 64x oversampling for three bits, 256x oversampling for four bits, ... Without noise shaping you need very high oversampling.
RPDAC obtains noise shaping by using DC-compensated patterns. In each used pattern the DC-component is exact, the DC error is removed.
Contact: krzysiek (at) podlesie.net. All suggestions are welcome.
git://git.podlesie.net/km/hw/rpdac.git
git://git.podlesie.net/km/hw/prng.git
git://git.podlesie.net/km/hw/esq.git
Please send comments on these web pages to krzysiek at podlesie period net.
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