/*
 * prng.v
 * Copyright (C) 2015  Krzysztof Mazur <krzysiek@podlesie.net>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

module prng(clk, reset, sync_in, out);
parameter RANDOM_BITS = 17;
parameter RANDOM_BITS_ORDER = 5;

/* polynomial from Maxim's PRNG application note */
parameter POLY = 31'h7a5bc2e3;
parameter POLY_BITS = 31;

input clk;				/* System clock */
input reset;				/* System reset */
input sync_in;				/* synchronization */

output [RANDOM_BITS - 1:0] out;		/* random output */

reg [RANDOM_BITS_ORDER - 1:0] phase = 0;
always @(posedge clk) begin
	if (reset)
		phase <= 0;
	else if (sync_in)
		phase <= 0;
	else if (phase < RANDOM_BITS)
		phase <= phase + 1;
	else
		phase <= phase;
end

/*
 * we need only RANDOM_BITS per cycle
 */
reg [POLY_BITS - 1:0] lfsr = 1;
always @(posedge clk) begin
	if (reset)
		lfsr <= 1;
	else if (phase < RANDOM_BITS)
		lfsr <= (lfsr >> 1) ^ (lfsr[0] ? POLY : 0);
	else
		lfsr <= lfsr;
end

assign out = lfsr[RANDOM_BITS - 1:0];

endmodule